Fraunhofer Institute for Integrated Circuits IIS
Fraunhofer Institute for Integrated Circuits IIS
Auf dem Bild ist ein Mikrochip zu sehen, der mit einem leuchtenden Symbol für künstliche Intelligenz (AI) versehen ist. Der Chip befindet sich auf einer komplexen Leiterplatte mit vielen elektrischen Verbindungen und leuchtenden Punkten.
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Neuromorphic Computing

A strategic initiative of Fraunhofer IIS

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Neuromorphic Computing

Energy-efficient smart chip design

AI solutions inspired by biological brains

Although Moore's Law still holds, the economic incentives for rapid scaling of semiconductor devices are diminishing due to rising costs in chip development and manufacturing. At the same time, the increasing demand for energy-efficient technologies for resource-intensive AI tasks and the growing global data volume require sustainable solutions. Neuromorphic computing, i.e., all hardware and software systems that mimic the functioning of the biological brain, offers a promising answer:

Neuromorphic computing is a key technology for significantly improving energy efficiency, allowing resource-intensive AI tasks to be executed directly on battery-powered devices. The combination of low latency and high energy efficiency enables real-time edge AI applications that require fast, local data processing. Unlike cloud-based approaches, edge AI also offers improved data privacy, addressing growing concerns in this area.

 

Innovation in hardware: Fraunhofer IIS shapes the future of AI

 

The goal of the »Neuromorphic Computing« initiative at Fraunhofer IIS is to integrate artificial intelligence directly into end devices and to develop the necessary algorithms and hardware. Scalable, configurable neuromorphic processor units and integrated circuits for DNNs and SNNs in CMOS technology are intended to enhance performance and reduce time-to-market through their high parallel processing and low latency.

To realize our ultra-energy-efficient and latency-optimized ASIC designs, we leverage our expertise in computer architectures, IC design, and neuroinformatics, complemented by specific application knowledge. This combination enables the development of innovative applications in the field of edge AI, which can be quickly implemented through our efficient hardware-software co-design flow.

Our offering: From consulting to the finished chip

With our extensive network of universities, research institutions, and industrial partners, we bridge the gap between the latest technology trends and industry-standard applications. We identify, develop, and implement the appropriate neuromorphic design for each use case. Our offering includes:

Feasibility studies

We advise you on all strategic and technological questions related to the complex topic of neuromorphic computing. We support you with neutral benchmarking tailored to your needs.

Inference accelerator IPs

We develop and license custom ASICs on which trained neural networks can be directly implemented, making your neural network ready for hardware.

Sensor ASICs with NPU

We handle the integration of sensor interfaces and the processing of sensor signals to evaluate analog sensors with high precision and cost-effectiveness.

Our strength: Synergies from science and practice

Neuromorphic computing is an interdisciplinary field that requires extensive expertise. Fraunhofer IIS brings exactly this expertise with in-depth knowledge in low-power IC design, neural network algorithms, software tools, and architecture design. Additionally, competencies in sensing, audio signal processing, image processing, communication, and localization enhance the technological portfolio. Long-standing partnerships with leading foundries and technology IP providers also ensure access to the necessary materials and components for CMOS processes.

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Low-Power IC-Design
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Our strength in low-power IC design for neuromorphic hardware is based on extensive experience in analog and mixed-signal circuit design for energy-autonomous applications. We leverage our comprehensive system knowledge as well as our expertise in semiconductor devices and processes for the design, qualification, and series testing of components. Our expertise in various semiconductor technologies and memory cells such as SRAM supports the selection of semiconductor processes. Additionally, we expand our knowledge in the design of non-volatile memory technologies (eNVM) through European projects. In-house developed tools for partial automation of analog design reduce development effort and allow for adjustments to different network sizes.

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We have extensive expertise in the design, training, and optimization of algorithms for neural networks (NNs). Our focus is on developing algorithms that efficiently reduce the computations of MAC (Multiply-Accumulate) operations and network parameters without compromising the accuracy of the models. Additionally, we emphasize hardware-aware training to ensure that our models run optimally on the available hardware, taking into account its specific characteristics and limitations.

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Our expertise includes the development and application of software tools for hardware/software co-design. This encompasses specialized tools such as hardware-aware training and inference tools, mappers and compilers, simulation tools, as well as tools for neuromorphic hardware generators for analog synthesis. These tools form a comprehensive ecosystem that is crucial for the efficient design and implementation of integrated systems that include both hardware and software.

Electronic circuit board close up.
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In the field of architecture design, we develop customized design architectures for mixed-signal inference accelerators. Our solutions are based on crossbar arrays and ASICs that are highly configurable and scalable. This enables us to create efficient and powerful systems for battery-powered devices.

Neuromorphic computing in application

Our customizable neuromorphic computing solutions are suitable for various AI applications and enable us to effectively address specific challenges in different industries. Examples include:

Intelligent sensor solutions

Intelligent sensor solutions utilize neuromorphic technology to process data directly at the source, reducing latency and energy consumption.

Communication technologies

Neuromorphic approaches significantly enhance signal processing and network optimization in communication technology, especially in satellite communication and IoT.

Smart wearables

In the field of smart wearables, better battery life and more accurate health monitoring are achieved through advanced sensors and real-time data processing.

Automotive

For the audio industry, more precise speech recognition and advanced audio processing are appealing – ideal for smart homes and consumer electronics. 

Autonomous systems

Autonomous systems greatly benefit from neuromorphic computing, as it enhances real-time environmental analysis and decision-making in autonomous vehicles, thereby increasing safety and efficiency.

Healthcare

In healthcare, our neuromorphic solutions open up new possibilities in medical diagnostics and patient monitoring through anomaly detection and predictive analytics.

Our references and projects

Get an overview here of our cross-industry projects, where innovative neuromorphic technologies and applications are already being developed:

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  • ADELIA – Analog deep learning inference accelerator

     

    The ADELIA project (Fraunhofer IIS and Fraunhofer IMPS) has participated in the challenge for disruptive innovation in energy-efficient AI hardware initiated by the German Federal Ministry of Education and Research (BMBF) in the category for ASIC-22FDX technology. ADELIA’s approach included the design of an accelerator architecture employing analog crossbars.

    ADELIA press release

  • ANDANTE – AI for new devices and technologies at the edge

    Project duration: 1.7.2020 – 30.6.2023
    Consortium: 8 partners from Germany, further 23 European partners
    Funding: ECSEL Joint Undertaking Initiative of the EU and German Federal Ministry of Education and Research (BMBF)
    Project website: https://www.andante-ai.eu/

     

    The goal of the ANDANTE project is to develop AI chips and platforms for edge applications, to develop the semiconductor technology basis for these chips and to realize relevant edge applications with these chips.

    Fraunhofer IIS is developing an analog mixed-signal hardware accelerator chip for neural networks (NN) as part of this project. The analog circuit technology makes it possible to implement the addition and multiplication calculations that are central to neural networks using the simplest circuits, thus achieving a significant advantage in terms of chip area requirements, energy efficiency and latency compared to digital concepts. The analog implementation comes along with some imperfections such as noise, manufacturing-related nonlinearities and component variances, which require special hardware-aware training and simulation tools. Fraunhofer IIS is therefore developing tools to obtain the smallest possible NN for real analog accelerators with desired accuracy and minimal energy consumption. During the project, in close collaboration with Fraunhofer EMFT and Fraunhofer IPMS, an AI chip will be developed and produced using 22FDX® Globalfoundries technology. The first pilot application to run on the AI chip and platform is voice activity detection (e.g. for smart speakers and smart home devices).

  • KI-FLEX – Reconfigurable hardware platform for AI-based sensor data processing for autonomous driving

    Project duration: 1.9.2019 – 31.8.2023
    Consortium: 8 partners from Germany
    Funding: German Federal Ministry of Education and Research (BMBF)
    Project website: www.iis.fraunhofer.de/ai-flex

     

    In the "KI-FLEX" project, eight project partners are developing a high-performance, energy-efficient hardware platform and the associated software framework for autonomous driving. The "KI-FLEX" platform is designed to reliably and quickly process and merge data from laser, camera and radar sensors in the car. Artificial intelligence (AI) methods are used for this purpose. The vehicle thus always has an accurate picture of the actual traffic conditions, can locate its own position in this environment, and on the basis of this information, make the right decision in every driving situation. 

    Fraunhofer IIS' contribution is the development of a flexible DLI accelerator core for the multi-core deep learning accelerator, which will be integrated together with other DLI accelerators into a flexible, future-proof ASIC. The architecture of the ASIC is designed in such a way that future improvements of NN architectures, i.e. emerging NN types and concepts, can still be realized with it. For this purpose, critical areas are specifically designed to be reconfigurable in order to build a bridge from the rigidity of an ASIC to the flexibility of an FPGA.

  • LODRIC – Low-power digital deep learning inference chip

    Project duration: 1.8.2021 – 31.12.2024
    Consortium: 3 partners from Germany
    Funding: Federal Ministry of Education and Research (BMBF)
    Project website: https://www.elektronikforschung.de/projekte/pilot-inno-lodric

     

    The LODRIC project extends the successful collaboration of the consortium, consisting of Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU) and Fraunhofer IIS, from the previous project "Lo3-ML".

    Its continuation is about the development of a design methodology for low-power digital AI chips with embedded non-volatile memory elements and its prototypical application on the basis of three different applications. Thereby, the main innovation of the project "Lo3-ML", namely the development of data-flow oriented computer architectures in combination with distributed, non-volatile weight memory and strongly (ternary) quantized weights shall be taken up and specifically methodically developed further.

    Fraunhofer IIS is represented with three disciplines: medical technology, digital circuit design, and embedded AI. The latter will expand its competencies in the area of hardware-aware training. In this context, a tool chain specific to accelerator technology will be further developed, which on the one hand achieves a significant reduction (optimization) of the neural network and on the other hand maintains its accuracy despite high quantization of the neuron weights through iterative retraining.

  • MANOLO – Trustworthy efficient AI for cloud-edge computing

    Project duration: 1.1.2024 – 31.12.2026 
    Consortium: 2 partners from Germany, further 16 European partners 
    Funding: Horizon Europe framework programme of the European Union
    Project website: https://manolo-project.eu/

     

    The vision of MANOLO is to deliver a complete and trustworthy stack of algorithms and tools to help AI systems reach better efficiency and seamless optimization in their operations. The focus is on energy-efficient training of AI models with quality-checked data and the execution of resource-efficient AI models on a wide range of devices for use on the edge and in the cloud.

    In the project, Fraunhofer IIS is focusing on bringing AI applications to the edge. To this end, algorithms and tools are being developed that search for and optimize suitable neural networks automatically (Neural Architecture Search, NAS). This results in efficient algorithms for deep neural networks (DNN) that can be executed on a wide variety of hardware. The plan is to test them in wearables and robots – both on traditional microcontrollers and on specialized AI accelerators. Fraunhofer IIS is also researching methods to generate spiking neural networks (SNN) from DNN models, thereby enabling the use of new types of neuromorphic algorithms.

  • NEUROKIT2E – Open-source deep learning platform for embedded hardware in europe

    Project duration: 1.6.2023 – 31.05.2026​
    Consortium: Four partners from Germany, 22 others from Europe
    Funding: KDT Joint Undertaking Initiative of the EU and the Federal Ministry of Education and Research (BMBF)

     

    NEUROKIT2E aims to develop an independent open-source framework for edge/embedded AI, supporting an international community of users and a wide range of applications. This European framework, specifically for embedded AI, is intended to be compatible with existing frameworks and facilitate the development and implementation of AI applications on embedded hardware.

    Fraunhofer IIS will contribute its multicore mixed-signal DNN inference accelerator architecture based on analog crossbar arrays for ultra-low power applications in NEUROKIT2E. Additionally, the development of a mapper and compiler toolchain, as well as tools for optimizing neural networks, will be included. This enables efficient design space exploration to identify the optimal architecture in terms of key performance indicators (KPIs) such as energy consumption, latency, and throughput for the specific application. Furthermore, Fraunhofer IIS will develop tools that allow efficient mapping of SNNs onto embedded hardware.

  • SEC-Learn – Sensor edge cloud for federated learning

    Project duration: 1.7.2020 – 31.12.2024
    Consortium: 11 Fraunhofer Institutes from the Groups for Microelectronics and ICT
    Funding: until 2021: InnoPush Program of the German Federal Ministry of Education and Research (BMBF); from 2022: Fraunhofer Executive Board Project

     

    In the SEC-Learn project, a system of distributed energy-efficient edge devices is being created that learn together to solve a complex signal processing problem using machine learning. The focus of the project is on the development of fast, energy- and space-efficient hardware accelerators for Spiking Neural Networks (SNN) on the one hand, and on their interconnection to form a federated system on the other hand, in which each device can act and learn autonomously, but shares its learning successes with all other devices through federated learning.

    This concept enables numerous applications, from autonomous driving to condition monitoring, where decentralized data processing through AI needs to be connected to a centralized system for training – without violating privacy or causing excessive power consumption and data traffic.

    The hardware accelerators used in the project are being developed under the coordination of Fraunhofer IIS in close cooperation with Fraunhofer EMFT and the EAS division of Fraunhofer IIS. To this end, Fraunhofer IIS is developing neuromorphic mixed-signal circuits for specialized neuron and synapse models at its Erlangen site, the associated software tools for hardware-aware training and simulation, and a scalable chip architecture that should make it possible to serve a wide variety of application problems in the future.

    More information about the SEC-Learn project 

Technical articles for download

Gain valuable insights, the latest findings, and practical information on the topic of neuromorphic computing.

AI goes Ultra-Low-Power
Neuromorphe Hardware
Elektronenhirn 4.0
Bitkom-Whitepaper »Future Computing«

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