2024

Erlangen, Germany: The nanoSPECTRAL chip is a chip-size spectrometer based on the nanoSPECTRAL technology developed at the Fraunhofer Institute for Integrated Circuits IIS. This chip offers an innovative solution for spectral analyses, making it possible to measure the optical spectrum of a wide variety of objects quickly and precisely – both in transmission and in reflection. What’s new is that the technology is compact, affordable, and easy to integrate into existing systems. This opens the door to new potential applications – from agriculture and the food industry to medical applications. The nanoSPECTRAL chip will be presented at electronica in Munich from November 12 to 15, 2024.

Erlangen, Germany: Radiation, vacuum, and substantial temperature fluctuations: extreme conditions prevail in space, presenting a tough challenge for satellite communications. With the Fraunhofer On-Board Processor (FOBP), experiments can be conducted in space to explore whether new technologies are operational under real conditions. The FOBP passed its final tests last week and has begun its service on board the Heinrich Hertz satellite of the German Space Agency at the German Aerospace Center (DLR).

At the beginning of 2024, Bernhard Niemann took over from his predecessor Michael Schlicht as Director of the Communication Systems division at the Fraunhofer Institute for Integrated Circuits IIS. Niemann has been working at Fraunhofer IIS for more than 20 years. He moved from the position of Head of the Broadband and Broadcast department to the role of division director.

The Fraunhofer Development Center X-ray Technology EZRT, a division of the Fraunhofer Institute for Integrated Circuits IIS, has developed a novel testing method for electric-vehicle batteries. In collaboration with Hochschule München University of Applied Sciences, the scientists have now showcased the AIR research project (a German acronym for traction battery inspection using X-rays), presented measurement results from preliminary studies, and classified the possibilities that could open up for private users once the research project has been completed.

For thirteen years, Prof. Peter Schneider has been the head of the Engineering of Adaptive Systems EAS division, part of the Fraunhofer Institute for Integrated Circuits IIS. On January 1, 2024, he was joined by electrical engineer Dr. Wolfgang Felber.

GRENOBLE, France – Feb. 27, 2024 – A new European Union consortium created to accelerate the development of next-generation, edge-AI technologies is installing cleanroom tools and gearing up to design, evaluate, test and fabricate new circuits from across Europe.

Erlangen, November 13, 2024: Fraunhofer IIS is the first technology supplier to implement WorldDAB’s new EWS/ASA alarm signaling standard into their digital radio DAB+ head-end and receiver solutions. The implementation was tested and demonstrated as an on-air showcase during the recent “Deutscher Warntag”. Public and private broadcasters as well as device manufacturers can now receive the innovation through a DAB ContentServer technology upgrade.

On January 18, 2024, the Bavarian Chip Design Center (BCDC) reached an important milestone on its path toward making Bavaria a leading location for innovation and excellence in chip design. As part of the Symposium on Chip Development – Greater Innovation through Chip Design, held at Fraunhofer IIS, Bavaria’s Minister of Economic Affairs Hubert Aiwanger presented the Center with a grant of 50 million euros.

The large language model of the OpenGPT-X research project is now available for download on Hugging Face: "Teuken-7B" has been trained from scratch in all 24 official languages of the European Union (EU) and contains seven billion parameters. Researchers and companies can leverage this commercially usable open source model for their own artificial intelligence (AI) applications. Funded by the German Federal Ministry of Economic Affairs and Climate Action (BMWK), the OpenGPT-X consortium – led by the Fraunhofer Institutes for Intelligent Analysis and Information Systems IAIS and for Integrated Circuits IIS – have developed a large language model that is open source and has a distinctly European perspective.

The pilot line for “Advanced Packaging and Heterogeneous Integration for Electronic Components and Systems” (APECS) marks a major leap forward in strengthening Europe’s semiconductor manufacturing capabilities and chiplet innovation as part of the EU Chips Act. By providing large industry players, SMEs, and start-ups with a facilitated access to cutting-edge technology, the APECS pilot line will establish a strong foundation for resilient and robust European semiconductor supply chains. Within APECS, the institutes collaborating in the Research Fab Microelectronics Germany (FMD) will work closely with European partners, to make a significant contribution to the European Union´s goals of increasing technological resilience, strengthening cross-border collaboration and enhancing its global competitiveness in semiconductor technologies. APECS is co-funded by the Chips Joint Undertaking and national funding authorities of Austria, Belgium, Finland, France, Germany, Greece, Portugal, Spain, through the “Chips for Europe” initiative. The overall funding for APECS amounts to € 730 million over 4.5 years.