New applications for electronics not only demand advanced performance and energy efficiency but also highly reliable ICs. This is especially true for safety critical applications, such as in automotive engineering, aviation and medical technology. Here designers are compelled to develop electronic devices with particularly high robustness and long lifetime. In order to meet the performance requirements, they increasingly rely on leading-edge technologies, which are very susceptible to degradation effects and consequently greater wear-out over the system’s lifetime. Fraunhofer IIS/EAS - one of the largest EDA institutions in Europe – is addressing the challenge of efficiently designing very reliable ICs in smaller technology nodes.

Usually, circuit designers minimize the risks of higher sensitivity to operating conditions and environmental stresses by applying larger design margins. This “over design” is no longer viable with today’s technologies. The solution to fully use the potential offered by advanced technologies is the establishment of aging simulations during the IC development process, which rely on accurate and technology specific degradation models. However, to this day such models are only partially available in existing simulation environments. For this reason, Fraunhofer IIS/EAS offers modeling services to fill this gap. Using their degradation models, designers can exactly predict silicon aging over several years of operation in real life applications. The models make it possible to verify and validate the function of an entire system under a variety of usage conditions. “Thus, our customers can be assured of a circuit’s functionality throughout the desired lifetime without costly over design and without the fear of future field failures”, points out Roland Jancke, head of the department for Design Methodology at Fraunhofer IIS/EAS.

The respective device degradation models are generated based on reliability measurement data and processed by advanced proprietary algorithms. The reliability models developed by Fraunhofer IIS/EAS include typical degradation effects like Hot Carrier Injection (HCI), Bias Temperature Instability (BTI) and Time Dependent Dielectric Breakdown. In addition, they also cover even more complex dependencies, such as saturation over time or voltage dependent time exponents, which are not available in commercial design tools. Fraunhofer IIS/EAS has even developed a fast yet accurate modeling solution for recovery effects, which appear in BTI degradation. “Our service offers a unique, comprehensive and much more significant lifetime prediction for digital and analog circuits in comparison to any other approach”, states Jancke.

The Fraunhofer IIS/EAS models can be used in all common commercially available design environments by supporting for example the circuit simulators of Cadence, Synopsys and Mentor Graphics. Circuit designers can run their simulator of choice to process realistic signal patterns in their application scenarios and ensure accurate reliability simulations, which match actual silicon behavior.

Together with EDATechForce, LLC, their exclusive distributor in the Americas, Fraunhofer IIS/EAS is offering these advanced modeling solutions worldwide. “Fraunhofer’s Degradation Modeling enables our customers to make accurate predictions on circuit behavior before products are delivered reducing expensive product recalls and field repairs, while increasing our customer’s profits.”, says Carl DeSalvo, President of EDATechForce. “And since they are available for all commercial design environments our customer’s no longer need to worry about conflicting degradation simulation results.”