Neuromorphic Computing

ADELIA – Analog deep learning inference accelerator

The ADELIA project (Fraunhofer IIS and Fraunhofer IMPS) has participated in the challenge for disruptive innovation in energy-efficient AI hardware initiated by the German Federal Ministry of Education and Research (BMBF) in the category for ASIC-22FDX technology. ADELIA’s approach included the design of an accelerator architecture employing analog crossbars.

ADELIA press release
ADELIA flyer

ANDANTE – AI for new devices and technologies at the edge

Project duration: 1.7.2020 – 30.6.2023
Consortium: 8 partners from Germany, further 23 European partners
Funding: ECSEL Joint Undertaking Initiative of the EU and German Federal Ministry of Education and Research (BMBF)
Project website: https://www.andante-ai.eu/

The goal of the ANDANTE project is to develop AI chips and platforms for edge applications, to develop the semiconductor technology basis for these chips and to realize relevant edge applications with these chips.

Fraunhofer IIS is developing an analog mixed-signal hardware accelerator chip for neural networks (NN) as part of this project. The analog circuit technology makes it possible to implement the addition and multiplication calculations that are central to neural networks using the simplest circuits, thus achieving a significant advantage in terms of chip area requirements, energy efficiency and latency compared to digital concepts. The analog implementation comes along with some imperfections such as noise, manufacturing-related nonlinearities and component variances, which require special hardware-aware training and simulation tools. Fraunhofer IIS is therefore developing tools to obtain the smallest possible NN for real analog accelerators with desired accuracy and minimal energy consumption. During the project, in close collaboration with Fraunhofer EMFT and Fraunhofer IPMS, an AI chip will be developed and produced using 22FDX® Globalfoundries technology. The first pilot application to run on the AI chip and platform is voice activity detection (e.g. for smart speakers and smart home devices).

KI-FLEX – Reconfigurable hardware platform for AI-based sensor data processing for autonomous driving

Project duration: 1.9.2019 – 31.8.2023
Consortium: 8 partners from Germany
Funding: German Federal Ministry of Education and Research (BMBF)
Project website: www.iis.fraunhofer.de/ai-flex

In the "KI-FLEX" project, eight project partners are developing a high-performance, energy-efficient hardware platform and the associated software framework for autonomous driving. The "KI-FLEX" platform is designed to reliably and quickly process and merge data from laser, camera and radar sensors in the car. Artificial intelligence (AI) methods are used for this purpose. The vehicle thus always has an accurate picture of the actual traffic conditions, can locate its own position in this environment, and on the basis of this information, make the right decision in every driving situation. 

Fraunhofer IIS' contribution is the development of a flexible DLI accelerator core for the multi-core deep learning accelerator, which will be integrated together with other DLI accelerators into a flexible, future-proof ASIC. The architecture of the ASIC is designed in such a way that future improvements of NN architectures, i.e. emerging NN types and concepts, can still be realized with it. For this purpose, critical areas are specifically designed to be reconfigurable in order to build a bridge from the rigidity of an ASIC to the flexibility of an FPGA.

LODRIC – Low-power digital deep learning inference chip

Project duration: 1.8.2021 – 31.12.2024
Consortium: 3 partners from Germany
Funding: Federal Ministry of Education and Research (BMBF)
Project website: https://www.elektronikforschung.de/projekte/pilot-inno-lodric

The LODRIC project extends the successful collaboration of the consortium, consisting of Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU) and Fraunhofer IIS, from the previous project "Lo3-ML".

Its continuation is about the development of a design methodology for low-power digital AI chips with embedded non-volatile memory elements and its prototypical application on the basis of three different applications. Thereby, the main innovation of the project "Lo3-ML", namely the development of data-flow oriented computer architectures in combination with distributed, non-volatile weight memory and strongly (ternary) quantized weights shall be taken up and specifically methodically developed further.

Fraunhofer IIS is represented with three disciplines: medical technology, digital circuit design, and embedded AI. The latter will expand its competencies in the area of hardware-aware training. In this context, a tool chain specific to accelerator technology will be further developed, which on the one hand achieves a significant reduction (optimization) of the neural network and on the other hand maintains its accuracy despite high quantization of the neuron weights through iterative retraining.

MANOLO – Trustworthy efficient AI for cloud-edge computing

Project duration: 1.1.2024 – 31.12.2026 
Consortium: 2 partners from Germany, further 16 European partners 
Funding: Horizon Europe framework programme of the European Union
Project website: https://manolo-project.eu/

The vision of MANOLO is to deliver a complete and trustworthy stack of algorithms and tools to help AI systems reach better efficiency and seamless optimization in their operations. The focus is on energy-efficient training of AI models with quality-checked data and the execution of resource-efficient AI models on a wide range of devices for use on the edge and in the cloud.

In the project, Fraunhofer IIS is focusing on bringing AI applications to the edge. To this end, algorithms and tools are being developed that search for and optimize suitable neural networks automatically (Neural Architecture Search, NAS). This results in efficient algorithms for deep neural networks (DNN) that can be executed on a wide variety of hardware. The plan is to test them in wearables and robots – both on traditional microcontrollers and on specialized AI accelerators. Fraunhofer IIS is also researching methods to generate spiking neural networks (SNN) from DNN models, thereby enabling the use of new types of neuromorphic algorithms.

NEUROKIT2E – Open-source deep learning platform for embedded hardware in europe

Project duration: 1.6.2023 – 31.05.2026​
Consortium: Four partners from Germany, 22 others from Europe
Funding: KDT Joint Undertaking Initiative of the EU and the Federal Ministry of Education and Research (BMBF)

NEUROKIT2E aims to develop an independent open-source framework for edge/embedded AI, supporting an international community of users and a wide range of applications. This European framework, specifically for embedded AI, is intended to be compatible with existing frameworks and facilitate the development and implementation of AI applications on embedded hardware.

Fraunhofer IIS will contribute its multicore mixed-signal DNN inference accelerator architecture based on analog crossbar arrays for ultra-low power applications in NEUROKIT2E. Additionally, the development of a mapper and compiler toolchain, as well as tools for optimizing neural networks, will be included. This enables efficient design space exploration to identify the optimal architecture in terms of key performance indicators (KPIs) such as energy consumption, latency, and throughput for the specific application. Furthermore, Fraunhofer IIS will develop tools that allow efficient mapping of SNNs onto embedded hardware.

SEC-Learn – Sensor edge cloud for federated learning

Project duration: 1.7.2020 – 31.12.2024
Consortium: 11 Fraunhofer Institutes from the Groups for Microelectronics and ICT
Funding: until 2021: InnoPush Program of the German Federal Ministry of Education and Research (BMBF); from 2022: Fraunhofer Executive Board Project

In the SEC-Learn project, a system of distributed energy-efficient edge devices is being created that learn together to solve a complex signal processing problem using machine learning. The focus of the project is on the development of fast, energy- and space-efficient hardware accelerators for Spiking Neural Networks (SNN) on the one hand, and on their interconnection to form a federated system on the other hand, in which each device can act and learn autonomously, but shares its learning successes with all other devices through federated learning.

This concept enables numerous applications, from autonomous driving to condition monitoring, where decentralized data processing through AI needs to be connected to a centralized system for training – without violating privacy or causing excessive power consumption and data traffic.

The hardware accelerators used in the project are being developed under the coordination of Fraunhofer IIS in close cooperation with Fraunhofer EMFT and the EAS division of Fraunhofer IIS. To this end, Fraunhofer IIS is developing neuromorphic mixed-signal circuits for specialized neuron and synapse models at its Erlangen site, the associated software tools for hardware-aware training and simulation, and a scalable chip architecture that should make it possible to serve a wide variety of application problems in the future.

More information about the SEC-Learn project 

SUSTAINET-inNOvAte – Seamless, secure, and resilient networks for the dynamic digital world

Project duration: 1.1.2025 – 31.12.2027 
Consortium: 3 Fraunhofer Institutes and 11 additional national project partners
Funding: German Federal Ministry of Education and Research

The project "SUSTAINET-inNOvAte" aims to develop a reliable and fault-tolerant communication infrastructure that enables secure, seamless, and energy-efficient connectivity in an increasingly digitalized world. By exploring resilient technologies and innovative network monitoring concepts, the project seeks to improve the resilience and sustainability of communication networks to ensure stable communication even in the event of failures or disasters.

In this project, Fraunhofer IIS investigates and demonstrates approaches to neuromorphic computing in the form of spiking neural networks (SNNs) for application in wireless communication systems. The goal is to analyze how potential SNN-based solutions provide advantages over conventional neural networks in specific contexts, thereby enabling applications with the highest energy efficiency and very low latency.